A semiconductor device is formed by cutting a plurality of semiconductor chips arranged in a matrix shape above a single silicon wafer using dicing and sealing the chips by packaging.
In a conventional semiconductor chip, a method of adhering a lower side device with the upper side device using a spacer or a method of misaligning the center of a chip adhered to an upper side from the center of a chip on the lower side are adopted when an electrical connection terminal arranged on the surface of the chip is connected using bonding wire etc in the case where for example the same chips are stacked using a die attach film in order to void connecting a chip adhered below.
In addition, there is a problem whereby a paste material which protrudes from an adhesion part of a pair of chips tends to creep up the side surface of a chip in the case of a package using a die attach paste, the creeping paste material reaches the top surface of the chip which degrades the quality of the semiconductor device.
For example, in a semiconductor device having a CoC (chip on chip) connection structure, when an underfill resin dripper between an upper side semiconductor chip and lower side conductor chip flows above an electrical connection terminal arranged on the surface of the lower side semiconductor chip, an electrical contact between the electrical connection terminal and bonding wire etc may be blocked. To deal with such a problem, a technique has been disclosed in Japanese Laid Open Patent No. 2014-103198 for example in which a dam pattern is arranged so as to enclose the electrical connection terminal.